The packaging of integrated circuit chips for use in computers or similar devices involves the attachment of integrated circuit semiconductor chips to printed circuit boards which printed circuit boards in turn are mounted in various computers or other type devices. The circuit boards have conductors formed thereon which provide the various power, ground and I/O signal lines to the integrated circuit chips.
There have been many different prior art proposals for connecting integrated circuit chips to printed circuit boards. The very large difference in thermal coefficient of expansion (TCE) between the silicon device, i.e. the chip, and the printed circuit board generally requires some intermediate device carrier. One such type of interconnection mounts the integrated circuit chip on a ceramic chip carrier or module, which module in turn is mounted on a circuit board. There may be one or more chips mounted on each device carrier or module and there may be one or more modules mounted on any given circuit board. In a particularly well known type of configuration of such mounting, the integrated circuit chip is mounted onto a ceramic module by "flip-chip" bonding wherein the I/O pads on the face of the chip are bonded to corresponding pads on the module, such connection being formed by use of solder bumps or solder balls normally using solder reflow techniques. Such connections are often referred to as C4 connections. The ceramic module conventionally has a wiring structure either on the surface thereof or more usually on the surface and also buried therein which fans out, and vias formed of conducting material pass through the module terminating on the opposite side thereof. Conventionally, the opposite side of the module is provided with an array of pins which pins in turn are positioned to be inserted into a complementary array of holes on a circuit board. This type of mounting of a module to a card is commonly known as "pin-in-hole" mounting. Mounting of a chip to module or module to card by these types of connections is shown in U.S. Pat. No. 4,415,025 assigned to IBM. The wiring "fans out" on the lower side of the carrier to about a 0.100" grid (at the present state of technology). This is a conventional type of interconnection between integrated circuit chips and printed circuit boards using "flip-chip" or solder ball technology to mount the chip to a ceramic chip carrier and using pin-in-hole technology to mount the ceramic carrier to a printed circuit board. A variation of this type of mounting using an interposer is shown in IBM Technical Disclosure Bulletin Volume 18, Number 5, Pages 1379-1380.
While this technique for connection of chips to boards is effective in many instances, it does have several drawbacks and limitations. One very serious drawback is the differential of the expansion of the ceramic chip carrier on one hand and the glass reinforced plastic printed circuit board on the other hand when the board and chip carrier are heated. Because of this differential of expansion, stress is created at the board/module interface, which can lead to material failure. This becomes more critical for larger modules (e.g. high I/O pin count) Another draw back to this type of mounting is the spacing requirements for pin and holes (e.g. 0.100" is typical). Large through holes in the card (typically 30-40 mils) require spacings of 75-100 mils thereby necessitating a rather large area of interconnection to the circuit board even though the spacing of the I/O pads on the integrated circuit chip are relatively closely spaced. Further, the pins and holes must be precisely aligned to assure proper interconnection.
One attempt to overcome these drawbacks is the so-called direct chip attached to the circuit board. This does have many advantages. However, in addition to the thermal mis-match, it does pose certain problems, since the spacing of the interconnect pads on the chip are so very close that they require very fine line patterns on the substrate to which the chip is to be attached. For example, because of the very high density of I/O pads on chips (i.e. their very close spacing, 0.010" being typical), the line widths and corresponding spacing that is required for this mounting can be very small, the line width required in some cases being as small as 0.001 inch, or less. While it is theoretically possible to achieve this fine line size and close spacing on a card, it would be very expensive to do so, especially with the quality and process controls necessary for commercial production. Since these fine line sizes and spacings are required only in the area of chip attachment and not on the rest of the circuit board, using this technology on the entire circuit board introduces substantially extra costs, and the fine lines required introduces reliability as well as cost problems in forming these fine lines at locations on the board, especially at locations other than the chip attachment areas, where it is not necessary to do so.
There have been several different attempts to overcome the various drawbacks of the direct chip attachments and other chip attachment techniques while retaining the use of chip carriers. One such proposal is shown in U.S. Pat. No. 4,202,007 in FIG. 6 thereof wherein a ceramic chip carrier which mounts a chip is mounted to the circuit board by means of solder ball interconnections. This overcomes the problem of the large area required for the spacing of pin and hole mounting. Moreover, the use of solder ball technology allows the interconnections of the ceramic carrier to the board to be closer together. Additionally, this frees up some board wiring channels which would be blocked by pins. However, this does not overcome the problem inherent in thermal mismatch between the ceramic carrier and the circuit board, i.e. the difference in the TCE's of both materials.
Other techniques for attachment of ceramic chip carriers to glass reinforced epoxy circuit boards (FR-4) are shown in IBM Technical Disclosure Bulletin Volume 18, Number 5, Pages 1440-1441 and IBM Technical Disclosure Bulletin Volume 20, Number 8, Pages 3090-3091.
In an attempt to overcome the problem of thermal mismatch between the chip carrier and the circuit board it has been proposed to fashion the chip carrier from a material similar to that of the circuit board. Such techniques are described in IBM Technical Disclosure Bulletin Volume 33, Number 2, Pages 15-16 and IBM Technical Disclosure Bulletin Volume 10, Number 12, Pages 1977-1978. However, both of these references require that the connections, at least for the signal I/O lines, be on the same side of the carrier as that to which the chip is mounted (Volume 33, Number 2 does show a pin mounting of the power and ground pins from the opposite side of the carrier to the carrier). These techniques do solve the problem of thermal mismatch between the chip carrier and the circuit board, but they require peripheral I/O bonding and an additional interposer between the chip and the chip carrier. IBM Technical Disclosure Bulletin Vol. 10, No. 12, requires peripheral attachment of the chip to an interposer (carrier 2) which is bonded to the chip carrier and then attached to the card. This peripheral bonding on the chip limits the I/O which can be placed on a small chip.
IBM Technical Disclosure Bulletin Vol. 33, No. 2, requires a peripheral attach of a flexible interposer between chip carrier and card and also has size and I/O limitations.